MESSAGE SIGNALED INTERRUPT

Hope you might have read my previous article "Interrupt journey  from hardware to software"

Due to increasing pressure on chipset and processor packages to reduce pin count, the need for interrupt pins is expected to diminish over time.Devices, due to pin constraints, may implement messages to increase performance. 

PCI Express endpoints uses INTx emulation (in-band messages) instead of IRQ pin assertion. Using INTx emulation requires interruptsharing among devices connected to the same node (PCI bridge) while MSI is unique (non-shared) and does not require BIOS configuration support. As a result, the PCI Express technology requires MSI support for better interrupt performance.

INTERRUPT DELIVERY MECHANISM

Legacy PCI Interrupt Delivery

   

This mechanism supports devices that must use PCI-Compatible interrupt signaling (i.e., INTA#, INTB#, INTC#, and INTD#) defined for the PCI bus. Legacy functions use one of the interrupt lines to signal an interrupt. An INTx# signal is asserted to request interrupt service and deasserted when the interrupt service accesses a device-specific register, thereby indicating the interrupt is being serviced.

Native PCI Express Interrupt Delivery 

Native PCI Express device use message signaled interrupt. A Message Signaled Interrupt is not a PCI express message instead it is a simple memory write transaction. This write is distinguished from normal write by target address which is reserved for MSI interrupt delivery.

           PCI Express and Legacy Interrupt Delivery

Message Signaled Interrupts (MSIs) are delivered to the Root Complex via memory write transactions. The MSI Capability register provides all the information that the device requires to signal MSIs. This register is set up by configuration software (PCI bus driver) and includes the following information:

• Target memory address
• Data Value to be written to the specified address location
• The number of messages that can be encoded into the data

         MSI Capability Register

MSI Configuration Process

The following list specifies the steps taken by software (PCI bus driver) to configure MSI interrupts for a PCI Express device.

1. At startup time, the configuration software scans the PCI bus(es) (referred to as bus enumeration) and discovers devices (i.e., it performs configuration reads for valid Vendor IDs). On discovering a PCI express function, the configuration software reads the Capabilities List Pointer to obtain the location of the first Capability register within the chain of registers.

2. The software then searches the capability register sets until it discovers the MSI Capability register set (Capability ID of 05h).

3. Software assigns a dword-aligned memory address to the device's Message Address register. This is the destination address of the memory write used when delivering an interrupt request.

4. Software checks the Multiple Message Capable field in the device's Message Control register to determine how many event-specific messages the device would like assigned to it.

5. The software then allocates a number of messages equal to or less than what the device requested. At a minimum, one message will be allocated to the device.

6. The software writes the base message data pattern into the device's Message Data register.

7. Finally, the software sets the MSI Enable bit in the device's Message Control register, thereby enabling it to generate interrupts using MSI memory writes.

Memory Write Transaction (MSI):

When the device must generate an interrupt request, it writes the Message Data register contents to the memory address specified in its Message Address register. Header fields need to filled.

MSI-x is a extension to MSI which supports additional vectors per function.

Reference: PCI Express System Architecture